Version in base suite: 1.0.12504.6-1 Base version: intel-graphics-compiler_1.0.12504.6-1 Target version: intel-graphics-compiler_1.0.12504.6-1+deb12u1 Base file: /srv/ftp-master.debian.org/ftp/pool/main/i/intel-graphics-compiler/intel-graphics-compiler_1.0.12504.6-1.dsc Target file: /srv/ftp-master.debian.org/policy/pool/main/i/intel-graphics-compiler/intel-graphics-compiler_1.0.12504.6-1+deb12u1.dsc changelog | 10 control | 2 patches/0001-Preinstalled-SPIRV-Tools-CMakeFile-fix.patch | 51 patches/0002-Changed-relative-paths-in-include-directives.patch | 524 ++++ patches/0003-Add-multi-indirect-byte-regioning-feature.patch | 162 + patches/0004-VC-subtarget-refactoring.patch | 1075 ++++++++++ patches/fix-relative-includes.patch | 15 patches/fix-spirv-check.diff | 13 patches/series | 7 9 files changed, 1827 insertions(+), 32 deletions(-) diff -Nru intel-graphics-compiler-1.0.12504.6/debian/changelog intel-graphics-compiler-1.0.12504.6/debian/changelog --- intel-graphics-compiler-1.0.12504.6/debian/changelog 2022-12-06 09:27:47.000000000 +0000 +++ intel-graphics-compiler-1.0.12504.6/debian/changelog 2023-11-17 12:34:30.000000000 +0000 @@ -1,3 +1,13 @@ +intel-graphics-compiler (1.0.12504.6-1+deb12u1) bookworm; urgency=medium + + * Replace patches with cherry-picked upstream commits. + * Cherry-pick fixes for compatibility with intel-vc-intrinsics 0.11.0. + (Closes: #1055874) + * Bump intel-vc-intrinsics build-dependency to 0.11.0. + * Upload to bookworm. + + -- Andreas Beckmann Fri, 17 Nov 2023 13:34:30 +0100 + intel-graphics-compiler (1.0.12504.6-1) unstable; urgency=medium [ Andreas Beckmann ] diff -Nru intel-graphics-compiler-1.0.12504.6/debian/control intel-graphics-compiler-1.0.12504.6/debian/control --- intel-graphics-compiler-1.0.12504.6/debian/control 2022-12-06 09:04:19.000000000 +0000 +++ intel-graphics-compiler-1.0.12504.6/debian/control 2023-11-17 12:34:30.000000000 +0000 @@ -15,7 +15,7 @@ zlib1g-dev, # keep the clang/llvm version in sync clang-14, - intel-vc-intrinsics-14-dev (>= 0.5.0), + intel-vc-intrinsics-14-dev (>= 0.11.0), liblld-14-dev, libllvmspirvlib-14-dev, libopencl-clang-14-dev, diff -Nru intel-graphics-compiler-1.0.12504.6/debian/patches/0001-Preinstalled-SPIRV-Tools-CMakeFile-fix.patch intel-graphics-compiler-1.0.12504.6/debian/patches/0001-Preinstalled-SPIRV-Tools-CMakeFile-fix.patch --- intel-graphics-compiler-1.0.12504.6/debian/patches/0001-Preinstalled-SPIRV-Tools-CMakeFile-fix.patch 1970-01-01 00:00:00.000000000 +0000 +++ intel-graphics-compiler-1.0.12504.6/debian/patches/0001-Preinstalled-SPIRV-Tools-CMakeFile-fix.patch 2023-11-17 12:34:30.000000000 +0000 @@ -0,0 +1,51 @@ +From 385f67c0b9a0eda6a65c56616e84bb2d612f82cf Mon Sep 17 00:00:00 2001 +From: Jakub Czarnecki +Date: Thu, 15 Dec 2022 12:07:06 +0000 +Subject: [PATCH] Preinstalled SPIRV-Tools CMakeFile fix + +Corrected typos and missing characters from the SPIRV-Tools CMakeFile, +added add_custom_target to allow marking preinstalled SPIRV-Tools as a +target. +--- + external/SPIRV-Tools/CMakeLists.txt | 11 ++++++----- + 1 file changed, 6 insertions(+), 5 deletions(-) + +diff --git a/external/SPIRV-Tools/CMakeLists.txt b/external/SPIRV-Tools/CMakeLists.txt +index 076079f7c..9afa5746c 100644 +--- a/external/SPIRV-Tools/CMakeLists.txt ++++ b/external/SPIRV-Tools/CMakeLists.txt +@@ -13,14 +13,14 @@ message(STATUS "============================ SPIRV-Tools project =============== + if(IGC_OPTION__SPIRV_TOOLS_MODE STREQUAL PREBUILDS_MODE_NAME) + + message(STATUS "[SPIRV-Tools] : IGC_OPTION__SPIRV_TOOLS_MODE set to Prebuilds") +- OPTION(IGC__OPTION_USE_PREINSTALLED_SPRIV_HEADERS OFF) ++ OPTION(IGC_OPTION__USE_PREINSTALLED_SPIRV_HEADERS OFF) + +- if(IGC_OPTION__USE_PREINSTALLED_SPRIV_HEADERS) +- message(STATUS "[SPIRV-Tools] : IGC__OPTION_USE_PREINSTALLED_SPRIV_HEADERS set to ON, using preinstalled SPIRV-Headers") ++ if(IGC_OPTION__USE_PREINSTALLED_SPIRV_HEADERS) ++ message(STATUS "[SPIRV-Tools] : IGC_OPTION__USE_PREINSTALLED_SPIRV_HEADERS set to ON, using preinstalled SPIRV-Headers") + message(STATUS "[SPIRV-Tools] : Using preinstalled SPIRV-Headers") + set(SPIRV-Headers_INCLUDE_DIR "/usr/include") + else() +- message(STATUS "[SPIRV-Tools] : IGC__OPTION_USE_PREINSTALLED_SPRIV_HEADERS set to OFF") ++ message(STATUS "[SPIRV-Tools] : IGC_OPTION__USE_PREINSTALLED_SPIRV_HEADERS set to OFF") + message(STATUS "[SPIRV-Tools] : Using default path ${CMAKE_CURRENT_SOURCE_DIR}/../../SPIRV-Headers") + set(SPIRV-Headers_INCLUDE_DIR "${CMAKE_CURRENT_SOURCE_DIR}/../../SPIRV-Headers/include") + endif() +@@ -29,10 +29,11 @@ if(IGC_OPTION__SPIRV_TOOLS_MODE STREQUAL PREBUILDS_MODE_NAME) + find_package(SPIRV-Tools REQUIRED COMPONENTS SPIRV-Tools) + message(STATUS "[SPIRV-Tools] : Found prebuilt SPIRV-Tools package in: ${SPIRV-Tools_CONFIG}") + +- set(SPIRV-Tools_ROOT_DIR "${SPIRV-Tools_DIR}../../..") ++ set(SPIRV-Tools_ROOT_DIR "${SPIRV-Tools_DIR}/../../..") + set(IGC_BUILD__SPIRV-Tools_DIR "${SPIRV-Tools_ROOT_DIR}") + + set(INCLUDE_DIRS_LIST "${SPIRV-Tools_ROOT_DIR}/include" "${SPIRV-Headers_INCLUDE_DIR}") ++ add_custom_target(SPIRV-Tools) + set_target_properties(SPIRV-Tools PROPERTIES INCLUDE_DIRECTORIES "${INCLUDE_DIRS_LIST}") + set(IGC_BUILD__PROJ__SPIRV-Tools SPIRV-Tools) + +-- +2.20.1 + diff -Nru intel-graphics-compiler-1.0.12504.6/debian/patches/0002-Changed-relative-paths-in-include-directives.patch intel-graphics-compiler-1.0.12504.6/debian/patches/0002-Changed-relative-paths-in-include-directives.patch --- intel-graphics-compiler-1.0.12504.6/debian/patches/0002-Changed-relative-paths-in-include-directives.patch 1970-01-01 00:00:00.000000000 +0000 +++ intel-graphics-compiler-1.0.12504.6/debian/patches/0002-Changed-relative-paths-in-include-directives.patch 2023-11-17 12:34:30.000000000 +0000 @@ -0,0 +1,524 @@ +From 344553ffd6f80dc717098235b1d2cf0d077f383d Mon Sep 17 00:00:00 2001 +From: Jakub Czarnecki +Date: Tue, 22 Nov 2022 10:54:50 +0000 +Subject: [PATCH] Changed relative paths in #include directives + +Changed relative paths to files in #include directives to their project +alternatives to avoid incorrect lookups. + +(cherry picked from commit 982d253e0a2bb24130f42fd7ad27b257bed183c3) +--- + IGC/AdaptorCommon/API/igc.h | 2 +- + IGC/AdaptorCommon/TypesLegalizationPass.cpp | 2 +- + IGC/AdaptorCommon/TypesLegalizationPass.hpp | 2 +- + IGC/AdaptorOCL/OCL/Patch/patch_parser.cpp | 4 ++-- + IGC/AdaptorOCL/OCL/Platform/cmd_media_caps_g8.h | 2 +- + IGC/AdaptorOCL/OCL/Platform/cmd_parser_g8.cpp | 6 +++--- + IGC/AdaptorOCL/OCL/Platform/cmd_parser_g8.h | 2 +- + IGC/AdaptorOCL/OCL/sp/sp_convert_g8.h | 8 ++++---- + IGC/AdaptorOCL/OCL/sp/sp_g8.cpp | 12 ++++++------ + IGC/AdaptorOCL/OCL/sp/sp_g8.h | 14 +++++++------- + IGC/AdaptorOCL/OCL/sp/spp_g8.cpp | 10 +++++----- + IGC/AdaptorOCL/OCL/sp/spp_g8.h | 2 +- + IGC/AdaptorOCL/OCL/sp/zebin_builder.cpp | 2 +- + IGC/AdaptorOCL/SPIRV/SPIRVInternal.h | 2 +- + IGC/Compiler/CISACodeGen/CISACodeGen.h | 2 +- + .../CISACodeGen/FoldKnownWorkGroupSizes.cpp | 6 +++--- + IGC/Compiler/CISACodeGen/Platform.hpp | 6 +++--- + IGC/Compiler/CodeGenPublic.h | 6 +++--- + IGC/Compiler/CodeGenPublicEnums.h | 2 +- + IGC/Compiler/CustomSafeOptPass.cpp | 2 +- + IGC/Compiler/Optimizer/GatingSimilarSamples.hpp | 2 +- + IGC/Compiler/igc_workaround.h | 2 +- + IGC/ElfPackager/main.cpp | 4 ++-- + IGC/GenISAIntrinsics/GenIntrinsics.cpp | 2 +- + IGC/LLVM3DBuilder/BuiltinsFrontend.hpp | 8 ++++---- + IGC/common/ShaderOverride.cpp | 2 +- + IGC/common/SystemThread.h | 2 +- + visa/FC_linker/PatchInfoDumper.cpp | 2 +- + visa/FC_linker/PatchInfoReader.cpp | 2 +- + visa/FC_linker/PatchInfoRecord.h | 2 +- + 30 files changed, 61 insertions(+), 61 deletions(-) + +diff --git a/IGC/AdaptorCommon/API/igc.h b/IGC/AdaptorCommon/API/igc.h +index e073ac387..b813ff6bb 100644 +--- a/IGC/AdaptorCommon/API/igc.h ++++ b/IGC/AdaptorCommon/API/igc.h +@@ -17,7 +17,7 @@ SPDX-License-Identifier: MIT + + #include + #include "../../common/EmUtils.h" +-#include "../IGC/Compiler/CodeGenPublicEnums.h" ++#include "../../Compiler/CodeGenPublicEnums.h" + // TODO: add all external declarations so that external projects only need + // to include this file only. + +diff --git a/IGC/AdaptorCommon/TypesLegalizationPass.cpp b/IGC/AdaptorCommon/TypesLegalizationPass.cpp +index 10da29ee2..8b40868cc 100644 +--- a/IGC/AdaptorCommon/TypesLegalizationPass.cpp ++++ b/IGC/AdaptorCommon/TypesLegalizationPass.cpp +@@ -7,7 +7,7 @@ SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ + + #include "TypesLegalizationPass.hpp" +-#include "../Compiler/IGCPassSupport.h" ++#include "Compiler/IGCPassSupport.h" + #include "Probe/Assertion.h" + + #include "common/LLVMWarningsPush.hpp" +diff --git a/IGC/AdaptorCommon/TypesLegalizationPass.hpp b/IGC/AdaptorCommon/TypesLegalizationPass.hpp +index 73bdf282a..c90bad772 100644 +--- a/IGC/AdaptorCommon/TypesLegalizationPass.hpp ++++ b/IGC/AdaptorCommon/TypesLegalizationPass.hpp +@@ -12,7 +12,7 @@ SPDX-License-Identifier: MIT + #include + #include + #include "common/LLVMWarningsPop.hpp" +-#include "../Compiler/IGCPassSupport.h" ++#include "Compiler/IGCPassSupport.h" + + + class TypesLegalizationPass: public llvm::FunctionPass,public llvm::InstVisitor +diff --git a/IGC/AdaptorOCL/OCL/Patch/patch_parser.cpp b/IGC/AdaptorOCL/OCL/Patch/patch_parser.cpp +index 2afc6c1b3..75c7e1484 100644 +--- a/IGC/AdaptorOCL/OCL/Patch/patch_parser.cpp ++++ b/IGC/AdaptorOCL/OCL/Patch/patch_parser.cpp +@@ -8,14 +8,14 @@ SPDX-License-Identifier: MIT + + #include + #include +-#include "../../3d/common/iStdLib/iStdLib.h" ++#include <3d/common/iStdLib/iStdLib.h> + #include "IGC/common/igc_debug.h" + #include "IGC/common/igc_regkeys.hpp" + #include "patch_g7.h" + #include "patch_g8.h" + #include "patch_g9.h" + #include "visa/include/RelocationInfo.h" +-#include "../sp/sp_debug.h" ++#include "OCL/sp/sp_debug.h" + #include "Probe/Assertion.h" + + namespace iOpenCL +diff --git a/IGC/AdaptorOCL/OCL/Platform/cmd_media_caps_g8.h b/IGC/AdaptorOCL/OCL/Platform/cmd_media_caps_g8.h +index 46d08e78c..9ac1faee1 100644 +--- a/IGC/AdaptorOCL/OCL/Platform/cmd_media_caps_g8.h ++++ b/IGC/AdaptorOCL/OCL/Platform/cmd_media_caps_g8.h +@@ -8,7 +8,7 @@ SPDX-License-Identifier: MIT + + #pragma once + +-#include "../sp/sp_types.h" ++#include "OCL/sp/sp_types.h" + + namespace G6HWC + { +diff --git a/IGC/AdaptorOCL/OCL/Platform/cmd_parser_g8.cpp b/IGC/AdaptorOCL/OCL/Platform/cmd_parser_g8.cpp +index 77532c664..413ebead2 100644 +--- a/IGC/AdaptorOCL/OCL/Platform/cmd_parser_g8.cpp ++++ b/IGC/AdaptorOCL/OCL/Platform/cmd_parser_g8.cpp +@@ -7,10 +7,10 @@ SPDX-License-Identifier: MIT + ============================= end_copyright_notice ===========================*/ + + #include "IGC/common/igc_debug.h" +-#include "../sp/sp_types.h" ++#include "OCL/sp/sp_types.h" + +-#include "../sp/sp_debug.h" +-#include "../inc/common/igfxfmid.h" ++#include "OCL/sp/sp_debug.h" ++#include "common/igfxfmid.h" + + #include "cmd_shared_def_g8.h" + #include "cmd_media_def_g8.h" +diff --git a/IGC/AdaptorOCL/OCL/Platform/cmd_parser_g8.h b/IGC/AdaptorOCL/OCL/Platform/cmd_parser_g8.h +index 970858da4..d83d09b2c 100644 +--- a/IGC/AdaptorOCL/OCL/Platform/cmd_parser_g8.h ++++ b/IGC/AdaptorOCL/OCL/Platform/cmd_parser_g8.h +@@ -9,7 +9,7 @@ SPDX-License-Identifier: MIT + #pragma once + + //#include "ContextTypes.h" +-#include "../inc/common/igfxfmid.h" ++#include "common/igfxfmid.h" + + namespace G6HWC + { +diff --git a/IGC/AdaptorOCL/OCL/sp/sp_convert_g8.h b/IGC/AdaptorOCL/OCL/sp/sp_convert_g8.h +index a7e36642e..cb93442c6 100644 +--- a/IGC/AdaptorOCL/OCL/sp/sp_convert_g8.h ++++ b/IGC/AdaptorOCL/OCL/sp/sp_convert_g8.h +@@ -10,11 +10,11 @@ SPDX-License-Identifier: MIT + + #include "inc/common/Compiler/API/ShaderTypesEnum.h" + #include "inc/common/Compiler/API/SurfaceFormats.h" +-#include "../Platform/cmd_media_enum_g8.h" +-#include "../Platform/cmd_shared_enum_g8.h" ++#include "OCL/Platform/cmd_media_enum_g8.h" ++#include "OCL/Platform/cmd_shared_enum_g8.h" + #include "patch_list.h" +-#include "../CommandStream/SamplerTypes.h" +-#include "../CommandStream/SurfaceTypes.h" ++#include "OCL/CommandStream/SamplerTypes.h" ++#include "OCL/CommandStream/SurfaceTypes.h" + + namespace iOpenCL + { +diff --git a/IGC/AdaptorOCL/OCL/sp/sp_g8.cpp b/IGC/AdaptorOCL/OCL/sp/sp_g8.cpp +index ca0ebac4b..6f8846280 100644 +--- a/IGC/AdaptorOCL/OCL/sp/sp_g8.cpp ++++ b/IGC/AdaptorOCL/OCL/sp/sp_g8.cpp +@@ -14,11 +14,11 @@ SPDX-License-Identifier: MIT + #include "sp_convert_g8.h" + #include "sp_debug.h" + +-#include "../util/BinaryStream.h" ++#include "OCL/util/BinaryStream.h" + +-#include "../Platform/cmd_shared_init_g8.h" +-#include "../Platform/cmd_media_init_g8.h" +-#include "../Platform/cmd_parser_g8.h" ++#include "OCL/Platform/cmd_shared_init_g8.h" ++#include "OCL/Platform/cmd_media_init_g8.h" ++#include "OCL/Platform/cmd_parser_g8.h" + + #include "common/allocator.h" + #include "common/igc_regkeys.hpp" +@@ -36,9 +36,9 @@ SPDX-License-Identifier: MIT + #include "patch_g7.h" + #include "patch_g8.h" + +-#include "../../../Compiler/CodeGenPublic.h" ++#include + +-#include "../../../visa/include/visaBuilder_interface.h" ++#include + + #include + #include +diff --git a/IGC/AdaptorOCL/OCL/sp/sp_g8.h b/IGC/AdaptorOCL/OCL/sp/sp_g8.h +index e6119fccc..5ff43f87a 100644 +--- a/IGC/AdaptorOCL/OCL/sp/sp_g8.h ++++ b/IGC/AdaptorOCL/OCL/sp/sp_g8.h +@@ -11,16 +11,16 @@ SPDX-License-Identifier: MIT + #include + #include + +-#include "../Platform/cmd_media_caps_g8.h" +-#include "../../inc/common/igfxfmid.h" ++#include "OCL/Platform/cmd_media_caps_g8.h" ++#include "common/igfxfmid.h" + +-#include "../CommandStream/SamplerTypes.h" +-#include "../CommandStream/SurfaceTypes.h" ++#include "OCL/CommandStream/SamplerTypes.h" ++#include "OCL/CommandStream/SurfaceTypes.h" + +-#include "../KernelAnnotations.hpp" +-#include "../util/BinaryStream.h" ++#include "OCL/KernelAnnotations.hpp" ++#include "OCL/util/BinaryStream.h" + +-#include "../Patch/patch_parser.h" ++#include "OCL/Patch/patch_parser.h" + #include "inc/common/Compiler/API/SurfaceFormats.h" + #include "common/shaderHash.hpp" + #include "usc.h" +diff --git a/IGC/AdaptorOCL/OCL/sp/spp_g8.cpp b/IGC/AdaptorOCL/OCL/sp/spp_g8.cpp +index bd948ce34..284173566 100644 +--- a/IGC/AdaptorOCL/OCL/sp/spp_g8.cpp ++++ b/IGC/AdaptorOCL/OCL/sp/spp_g8.cpp +@@ -8,12 +8,12 @@ SPDX-License-Identifier: MIT + + #include "llvm/Config/llvm-config.h" + #include "spp_g8.h" +-#include "../../../Compiler/CodeGenPublic.h" ++#include "Compiler/CodeGenPublic.h" + #include "program_debug_data.h" +-#include "../../../common/SystemThread.h" +-#include "../../../common/Types.hpp" +-#include "../../../common/shaderOverride.hpp" +-#include "../../../Compiler/CISACodeGen/OpenCLKernelCodeGen.hpp" ++#include "IGC/common/SystemThread.h" ++#include "IGC/common/Types.hpp" ++#include "IGC/common/shaderOverride.hpp" ++#include "Compiler/CISACodeGen/OpenCLKernelCodeGen.hpp" + + #include + #include +diff --git a/IGC/AdaptorOCL/OCL/sp/spp_g8.h b/IGC/AdaptorOCL/OCL/sp/spp_g8.h +index 86d04cd32..c863e67c3 100644 +--- a/IGC/AdaptorOCL/OCL/sp/spp_g8.h ++++ b/IGC/AdaptorOCL/OCL/sp/spp_g8.h +@@ -12,7 +12,7 @@ SPDX-License-Identifier: MIT + #pragma once + + #include +-#include "../util/BinaryStream.h" ++#include "OCL/util/BinaryStream.h" + #include "usc.h" + #include "sp_g8.h" + #include "zebin_builder.hpp" +diff --git a/IGC/AdaptorOCL/OCL/sp/zebin_builder.cpp b/IGC/AdaptorOCL/OCL/sp/zebin_builder.cpp +index a02662126..fbe2ee7ed 100644 +--- a/IGC/AdaptorOCL/OCL/sp/zebin_builder.cpp ++++ b/IGC/AdaptorOCL/OCL/sp/zebin_builder.cpp +@@ -8,7 +8,7 @@ SPDX-License-Identifier: MIT + + #include "zebin_builder.hpp" + +-#include "../../../Compiler/CodeGenPublic.h" ++#include "Compiler/CodeGenPublic.h" + + #include "common/LLVMWarningsPush.hpp" + #include "llvm/ADT/SmallVector.h" +diff --git a/IGC/AdaptorOCL/SPIRV/SPIRVInternal.h b/IGC/AdaptorOCL/SPIRV/SPIRVInternal.h +index e1f425937..82e67d2e6 100644 +--- a/IGC/AdaptorOCL/SPIRV/SPIRVInternal.h ++++ b/IGC/AdaptorOCL/SPIRV/SPIRVInternal.h +@@ -76,7 +76,7 @@ THE SOFTWARE. + + #include "common/LLVMWarningsPop.hpp" + +-#include "../../inc/common/UFO/portable_compiler.h" ++#include "common/UFO/portable_compiler.h" + + #include + #include +diff --git a/IGC/Compiler/CISACodeGen/CISACodeGen.h b/IGC/Compiler/CISACodeGen/CISACodeGen.h +index 9f661ca09..3b5bf0a93 100644 +--- a/IGC/Compiler/CISACodeGen/CISACodeGen.h ++++ b/IGC/Compiler/CISACodeGen/CISACodeGen.h +@@ -9,7 +9,7 @@ SPDX-License-Identifier: MIT + #pragma once + #include "Compiler/CodeGenPublic.h" + #include "visaBuilder_interface.h" +-#include "../../inc/common/UFO/portable_compiler.h" ++#include "common/UFO/portable_compiler.h" + + namespace USC + { +diff --git a/IGC/Compiler/CISACodeGen/FoldKnownWorkGroupSizes.cpp b/IGC/Compiler/CISACodeGen/FoldKnownWorkGroupSizes.cpp +index 97dba1448..070ff4a0a 100644 +--- a/IGC/Compiler/CISACodeGen/FoldKnownWorkGroupSizes.cpp ++++ b/IGC/Compiler/CISACodeGen/FoldKnownWorkGroupSizes.cpp +@@ -8,9 +8,9 @@ SPDX-License-Identifier: MIT + + #include "Compiler/Optimizer/OpenCLPasses/WIFuncs/WIFuncsAnalysis.hpp" + #include "FoldKnownWorkGroupSizes.h" +-#include "../IGCPassSupport.h" +-#include "../CodeGenPublic.h" +-#include "../MetaDataApi/MetaDataApi.h" ++#include "Compiler/IGCPassSupport.h" ++#include "Compiler/CodeGenPublic.h" ++#include "Compiler/MetaDataApi/MetaDataApi.h" + + #include "LLVMWarningsPush.hpp" + #include "llvm/IR/Function.h" +diff --git a/IGC/Compiler/CISACodeGen/Platform.hpp b/IGC/Compiler/CISACodeGen/Platform.hpp +index 470ddf25c..241d507c4 100644 +--- a/IGC/Compiler/CISACodeGen/Platform.hpp ++++ b/IGC/Compiler/CISACodeGen/Platform.hpp +@@ -15,9 +15,9 @@ SPDX-License-Identifier: MIT + #include "Probe/Assertion.h" + #include "common/igc_regkeys.hpp" + +-#include "../../../skuwa/iacm_g10_rev_id.h" +-#include "../../../skuwa/iacm_g11_rev_id.h" +-#include "../../../skuwa/iacm_g12_rev_id.h" ++#include "skuwa/iacm_g10_rev_id.h" ++#include "skuwa/iacm_g11_rev_id.h" ++#include "skuwa/iacm_g12_rev_id.h" + + namespace IGC + { +diff --git a/IGC/Compiler/CodeGenPublic.h b/IGC/Compiler/CodeGenPublic.h +index bb82d1f45..c7bae550b 100644 +--- a/IGC/Compiler/CodeGenPublic.h ++++ b/IGC/Compiler/CodeGenPublic.h +@@ -32,9 +32,9 @@ SPDX-License-Identifier: MIT + #include "visa/include/RelocationInfo.h" + #include "ZEBinWriter/zebin/source/autogen/ZEInfo.hpp" + +-#include "../AdaptorOCL/OCL/sp/spp_g8.h" +-#include "../GenISAIntrinsics/GenIntrinsics.h" +-#include "../GenISAIntrinsics/GenIntrinsicInst.h" ++#include "AdaptorOCL/OCL/sp/spp_g8.h" ++#include "GenISAIntrinsics/GenIntrinsics.h" ++#include "GenISAIntrinsics/GenIntrinsicInst.h" + #include "common/LLVMWarningsPush.hpp" + #include + #include +diff --git a/IGC/Compiler/CodeGenPublicEnums.h b/IGC/Compiler/CodeGenPublicEnums.h +index 992cfd245..ca44dd061 100644 +--- a/IGC/Compiler/CodeGenPublicEnums.h ++++ b/IGC/Compiler/CodeGenPublicEnums.h +@@ -9,7 +9,7 @@ SPDX-License-Identifier: MIT + #ifndef CODE_GEN_PUBLIC_ENUMS_H_ + #define CODE_GEN_PUBLIC_ENUMS_H_ + +-#include "../IGC/common/EmUtils.h" ++#include "../common/EmUtils.h" + + namespace IGC + { +diff --git a/IGC/Compiler/CustomSafeOptPass.cpp b/IGC/Compiler/CustomSafeOptPass.cpp +index f256aa1ad..31e6d53fd 100644 +--- a/IGC/Compiler/CustomSafeOptPass.cpp ++++ b/IGC/Compiler/CustomSafeOptPass.cpp +@@ -86,7 +86,7 @@ cmp+sel to avoid expensive VxH mov. + #include + #include "common/LLVMWarningsPop.hpp" + #include +-#include "../inc/common/secure_mem.h" ++#include "common/secure_mem.h" + #include "Probe/Assertion.h" + + using namespace llvm; +diff --git a/IGC/Compiler/Optimizer/GatingSimilarSamples.hpp b/IGC/Compiler/Optimizer/GatingSimilarSamples.hpp +index 7305daacc..723f1fa1f 100644 +--- a/IGC/Compiler/Optimizer/GatingSimilarSamples.hpp ++++ b/IGC/Compiler/Optimizer/GatingSimilarSamples.hpp +@@ -8,7 +8,7 @@ SPDX-License-Identifier: MIT + + #pragma once + +-#include "../IGCPassSupport.h" ++#include "Compiler/IGCPassSupport.h" + #include "Compiler/CodeGenPublic.h" + #include "common/LLVMWarningsPush.hpp" + #include "llvm/Pass.h" +diff --git a/IGC/Compiler/igc_workaround.h b/IGC/Compiler/igc_workaround.h +index edd03e50f..5d43c320b 100644 +--- a/IGC/Compiler/igc_workaround.h ++++ b/IGC/Compiler/igc_workaround.h +@@ -10,7 +10,7 @@ SPDX-License-Identifier: MIT + + #include "inc/common/sku_wa.h" + #include "inc/common/igfxfmid.h" +-#include "../../skuwa/wa_def.h" ++#include "skuwa/wa_def.h" + #include "Compiler/CISACodeGen/Platform.hpp" + + namespace IGC +diff --git a/IGC/ElfPackager/main.cpp b/IGC/ElfPackager/main.cpp +index ae85a997c..1f350a3d0 100644 +--- a/IGC/ElfPackager/main.cpp ++++ b/IGC/ElfPackager/main.cpp +@@ -34,14 +34,14 @@ SPDX-License-Identifier: MIT + #include "llvmWrapper/ADT/STLExtras.h" + + #include "common/LLVMWarningsPop.hpp" +-#include "../GenISAIntrinsics/GenIntrinsics.h" ++#include "GenISAIntrinsics/GenIntrinsics.h" + + #include "ElfReader.h" + #include "ElfWriter.h" + + #include "CLElfTypes.h" + +-#include "../AdaptorOCL/OCL/LoadBuffer.h" ++#include "AdaptorOCL/OCL/LoadBuffer.h" + + #include + #include +diff --git a/IGC/GenISAIntrinsics/GenIntrinsics.cpp b/IGC/GenISAIntrinsics/GenIntrinsics.cpp +index 48c6f2096..72f388b45 100644 +--- a/IGC/GenISAIntrinsics/GenIntrinsics.cpp ++++ b/IGC/GenISAIntrinsics/GenIntrinsics.cpp +@@ -18,7 +18,7 @@ SPDX-License-Identifier: MIT + #include + #include + #include "common/LLVMWarningsPop.hpp" +-#include "../../inc/common/UFO/portable_compiler.h" ++#include "inc/common/UFO/portable_compiler.h" + #include + #include "Probe/Assertion.h" + +diff --git a/IGC/LLVM3DBuilder/BuiltinsFrontend.hpp b/IGC/LLVM3DBuilder/BuiltinsFrontend.hpp +index 6eb902778..65a50844f 100644 +--- a/IGC/LLVM3DBuilder/BuiltinsFrontend.hpp ++++ b/IGC/LLVM3DBuilder/BuiltinsFrontend.hpp +@@ -22,10 +22,10 @@ SPDX-License-Identifier: MIT + #include "inc/common/Compiler/API/SurfaceFormats.h" + #include "inc/common/igfxfmid.h" + #include "common/IGCIRBuilder.h" +-#include "../common/EmUtils.h" +-#include "../../../skuwa/iacm_g10_rev_id.h" +-#include "../../../skuwa/iacm_g11_rev_id.h" +-#include "../../../skuwa/iacm_g12_rev_id.h" ++#include "common/EmUtils.h" ++#include "skuwa/iacm_g10_rev_id.h" ++#include "skuwa/iacm_g11_rev_id.h" ++#include "skuwa/iacm_g12_rev_id.h" + + namespace llvm { + class GenIntrinsicInst; +diff --git a/IGC/common/ShaderOverride.cpp b/IGC/common/ShaderOverride.cpp +index e9978662d..d8f7f01af 100644 +--- a/IGC/common/ShaderOverride.cpp ++++ b/IGC/common/ShaderOverride.cpp +@@ -6,7 +6,7 @@ SPDX-License-Identifier: MIT + + ============================= end_copyright_notice ===========================*/ + +-#include "../../../visa/iga/IGALibrary/api/igad.h" ++#include "visa/iga/IGALibrary/api/igad.h" + #include + #include + #include +diff --git a/IGC/common/SystemThread.h b/IGC/common/SystemThread.h +index 7a8daca9b..39f94bb7a 100644 +--- a/IGC/common/SystemThread.h ++++ b/IGC/common/SystemThread.h +@@ -29,7 +29,7 @@ SPDX-License-Identifier: MIT + + #include "usc.h" + +-#include "../AdaptorOCL/OCL/LoadBuffer.h" ++#include "AdaptorOCL/OCL/LoadBuffer.h" + #include "Compiler/CISACodeGen/Platform.hpp" + #include "common/debug/Debug.hpp" + #include "Probe/Assertion.h" +diff --git a/visa/FC_linker/PatchInfoDumper.cpp b/visa/FC_linker/PatchInfoDumper.cpp +index bd25083af..fc4db6d7c 100644 +--- a/visa/FC_linker/PatchInfoDumper.cpp ++++ b/visa/FC_linker/PatchInfoDumper.cpp +@@ -17,7 +17,7 @@ SPDX-License-Identifier: MIT + #include + #include + +-#include "../PatchInfo.h" ++#include "visa/PatchInfo.h" + + namespace { + +diff --git a/visa/FC_linker/PatchInfoReader.cpp b/visa/FC_linker/PatchInfoReader.cpp +index e0d001c77..d7685aad9 100644 +--- a/visa/FC_linker/PatchInfoReader.cpp ++++ b/visa/FC_linker/PatchInfoReader.cpp +@@ -13,7 +13,7 @@ SPDX-License-Identifier: MIT + #include + #include + +-#include "../PatchInfo.h" ++#include "visa/PatchInfo.h" + #include "PatchInfoRecord.h" + #include "PatchInfoReader.h" + +diff --git a/visa/FC_linker/PatchInfoRecord.h b/visa/FC_linker/PatchInfoRecord.h +index 5b99605d2..b29e98a2a 100644 +--- a/visa/FC_linker/PatchInfoRecord.h ++++ b/visa/FC_linker/PatchInfoRecord.h +@@ -24,7 +24,7 @@ SPDX-License-Identifier: MIT + #include + #include + +-#include "../PatchInfo.h" ++#include "visa/PatchInfo.h" + + namespace cm { + +-- +2.20.1 + diff -Nru intel-graphics-compiler-1.0.12504.6/debian/patches/0003-Add-multi-indirect-byte-regioning-feature.patch intel-graphics-compiler-1.0.12504.6/debian/patches/0003-Add-multi-indirect-byte-regioning-feature.patch --- intel-graphics-compiler-1.0.12504.6/debian/patches/0003-Add-multi-indirect-byte-regioning-feature.patch 1970-01-01 00:00:00.000000000 +0000 +++ intel-graphics-compiler-1.0.12504.6/debian/patches/0003-Add-multi-indirect-byte-regioning-feature.patch 2023-11-17 12:34:30.000000000 +0000 @@ -0,0 +1,162 @@ +From 3a80463648e0bf67391cf72bf418bd12b8b0eb30 Mon Sep 17 00:00:00 2001 +From: "Shelegov, Maksim" +Date: Thu, 10 Nov 2022 22:11:09 +0000 +Subject: [PATCH] Add multi indirect byte regioning feature + +Define the subtarget feature correctly +--- + IGC/VectorCompiler/lib/GenXCodeGen/GenX.td | 19 +++++++++++++++++++ + .../lib/GenXCodeGen/GenXSubtarget.h | 9 +++++++-- + 2 files changed, 26 insertions(+), 2 deletions(-) + +diff --git a/IGC/VectorCompiler/lib/GenXCodeGen/GenX.td b/IGC/VectorCompiler/lib/GenXCodeGen/GenX.td +index e011a673d..3633657fa 100644 +--- a/IGC/VectorCompiler/lib/GenXCodeGen/GenX.td ++++ b/IGC/VectorCompiler/lib/GenXCodeGen/GenX.td +@@ -160,6 +160,10 @@ def WarnCallable : SubtargetFeature<"warn_callable", "WarnCallable", + def OCLRuntime : SubtargetFeature<"ocl_runtime", "OCLRuntime", "true", + "Prepare structures for OCL runtime">; + ++def FeatureMultiIndirectByteRegioning : SubtargetFeature<"multi_indirect_byte_regioning", ++ "HasMultiIndirectByteRegioning", ++ "true", ++ "Vx1 and VxH indirect addressing for Byte datatypes">; + + //===----------------------------------------------------------------------===// + // GenX processors supported. +@@ -175,6 +179,7 @@ def : Proc<"BDW", [FeatureLongLong, FeatureSwitchjmp, + FeatureFP64, + FeatureIEEEDivSqrt, + FeatureHasPackedFloat, ++ FeatureMultiIndirectByteRegioning, + FeatureHWTIDFromPredef]>; + def : Proc<"SKL", [FeatureLongLong, FeatureSwitchjmp, + FeatureIntDivRem32, +@@ -184,6 +189,7 @@ def : Proc<"SKL", [FeatureLongLong, FeatureSwitchjmp, + FeatureIEEEDivSqrt, + FeatureHasPackedFloat, + FeatureHWTIDFromPredef, ++ FeatureMultiIndirectByteRegioning, + FeaturePreemption]>; + def : Proc<"BXT", [FeatureLongLong, FeatureSwitchjmp, + FeatureIntDivRem32, +@@ -192,6 +198,7 @@ def : Proc<"BXT", [FeatureLongLong, FeatureSwitchjmp, + FeatureFP64, + FeatureHasPackedFloat, + FeatureHWTIDFromPredef, ++ FeatureMultiIndirectByteRegioning, + FeaturePreemption]>; + def : Proc<"KBL", [FeatureLongLong, FeatureSwitchjmp, + FeatureIntDivRem32, +@@ -201,6 +208,7 @@ def : Proc<"KBL", [FeatureLongLong, FeatureSwitchjmp, + FeatureIEEEDivSqrt, + FeatureHasPackedFloat, + FeatureHWTIDFromPredef, ++ FeatureMultiIndirectByteRegioning, + FeaturePreemption]>; + def : Proc<"GLK", [FeatureLongLong, FeatureSwitchjmp, + FeatureIntDivRem32, +@@ -209,27 +217,32 @@ def : Proc<"GLK", [FeatureLongLong, FeatureSwitchjmp, + FeatureFP64, + FeatureHasPackedFloat, + FeatureHWTIDFromPredef, ++ FeatureMultiIndirectByteRegioning, + FeaturePreemption]>; + def : Proc<"ICLLP", [FeatureLongLongEmulation, FeatureSwitchjmp, + FeatureIntDivRem32, FeatureInstrBitRotate, + FeatureIEEEDivSqrt, + FeatureHWTIDFromPredef, + FeatureHasPackedFloat, ++ FeatureMultiIndirectByteRegioning, + FeaturePreemption]>; + def : Proc<"TGLLP", [FeatureLongLongEmulation, FeatureIntDivRem32, + FeatureInstrBitRotate, FeatureWAFusedEUNoMask, + FeatureHWTIDFromPredef, + FeatureHasPackedFloat, ++ FeatureMultiIndirectByteRegioning, + FeaturePreemption, FeatureFusedEU]>; + def : Proc<"RKL", [FeatureLongLongEmulation, FeatureIntDivRem32, + FeatureInstrBitRotate, FeatureWAFusedEUNoMask, + FeatureHWTIDFromPredef, + FeatureHasPackedFloat, ++ FeatureMultiIndirectByteRegioning, + FeaturePreemption, FeatureFusedEU]>; + def : Proc<"DG1", [FeatureLongLongEmulation, FeatureIntDivRem32, + FeatureInstrBitRotate, FeatureWAFusedEUNoMask, + FeatureHWTIDFromPredef, + FeatureHasPackedFloat, ++ FeatureMultiIndirectByteRegioning, + FeaturePreemption, FeatureFusedEU]>; + def : Proc<"XEHP", [FeatureLongLong, + FeatureInstrAdd64, +@@ -237,26 +250,31 @@ def : Proc<"XEHP", [FeatureLongLong, + FeatureIEEEDivSqrt, + FeatureThreadPayloadInMemory, + FeatureHasPackedFloat, ++ FeatureMultiIndirectByteRegioning, + FeatureInstrBitRotate, FeatureFusedEU]>; + def : Proc<"ADLS", [FeatureLongLongEmulation, FeatureIntDivRem32, + FeatureInstrBitRotate, FeatureWAFusedEUNoMask, + FeatureHasPackedFloat, + FeatureHWTIDFromPredef, ++ FeatureMultiIndirectByteRegioning, + FeaturePreemption, FeatureFusedEU]>; + def : Proc<"ADLP", [FeatureLongLongEmulation, FeatureIntDivRem32, + FeatureInstrBitRotate, FeatureWAFusedEUNoMask, + FeatureHasPackedFloat, + FeatureHWTIDFromPredef, ++ FeatureMultiIndirectByteRegioning, + FeaturePreemption, FeatureFusedEU]>; + def : Proc<"ADLN", [FeatureLongLongEmulation, FeatureIntDivRem32, + FeatureInstrBitRotate, FeatureWAFusedEUNoMask, + FeatureHasPackedFloat, + FeatureHWTIDFromPredef, ++ FeatureMultiIndirectByteRegioning, + FeaturePreemption, FeatureFusedEU]>; + def : Proc<"DG2", [FeatureLongLongEmulation, + FeatureThreadPayloadInMemory, + FeatureHasPackedFloat, + FeatureInstrBitRotate, ++ FeatureMultiIndirectByteRegioning, + FeatureHasLSC, FeatureFusedEU]>; + def : Proc<"PVC", [FeatureLongLong, FeatureGRFByteSize64, + FeatureLSCMaxWidth32, +@@ -298,6 +316,7 @@ def : Proc<"MTL", [FeatureLongLongEmulation, + FeatureThreadPayloadInMemory, + FeatureInstrBitRotate, + FeatureBfMixedModeWidth16, ++ FeatureMultiIndirectByteRegioning, + FeatureHasLSC, FeatureFusedEU]>; + + def GenX : Target { +diff --git a/IGC/VectorCompiler/lib/GenXCodeGen/GenXSubtarget.h b/IGC/VectorCompiler/lib/GenXCodeGen/GenXSubtarget.h +index 802b9b006..121b4d0a5 100644 +--- a/IGC/VectorCompiler/lib/GenXCodeGen/GenXSubtarget.h ++++ b/IGC/VectorCompiler/lib/GenXCodeGen/GenXSubtarget.h +@@ -179,6 +179,9 @@ private: + // Has L3 flush on GPU-scope invalidate. + bool HasL3FlushOnGPUScopeInvalidate = false; + ++ // True if Vx1 and VxH indirect addressing are allowed for Byte datatypes ++ bool HasMultiIndirectByteRegioning = false; ++ + // Shows which surface should we use for stack + PreDefined_Surface StackSurf; + +@@ -375,9 +378,11 @@ public: + return hasIndirectGRFCrossing() && !isPVC(); + } + +- /// * hasMultiIndirectByteRegioning - true if target supports an mutli ++ /// * hasMultiIndirectByteRegioning - true if target supports an multi + /// indirect regions with byte type +- bool hasMultiIndirectByteRegioning() const { return !isPVC(); } ++ bool hasMultiIndirectByteRegioning() const { ++ return HasMultiIndirectByteRegioning; ++ }; + + bool hasNBarrier() const { return GenXVariant >= XE_PVC; } + +-- +2.20.1 + diff -Nru intel-graphics-compiler-1.0.12504.6/debian/patches/0004-VC-subtarget-refactoring.patch intel-graphics-compiler-1.0.12504.6/debian/patches/0004-VC-subtarget-refactoring.patch --- intel-graphics-compiler-1.0.12504.6/debian/patches/0004-VC-subtarget-refactoring.patch 1970-01-01 00:00:00.000000000 +0000 +++ intel-graphics-compiler-1.0.12504.6/debian/patches/0004-VC-subtarget-refactoring.patch 2023-11-17 12:34:30.000000000 +0000 @@ -0,0 +1,1075 @@ +From 916a01be779ad4280541fc1a83a98182c441569e Mon Sep 17 00:00:00 2001 +From: Victor Mustya +Date: Wed, 16 Nov 2022 05:59:08 +0000 +Subject: [PATCH] VC subtarget refactoring + +Refactor VC subtargets to reduce copy-paste +--- + .../cmake/supported_platforms_list.cmake | 34 +- + .../igcdeps/src/TranslationInterface.cpp | 48 ++- + IGC/VectorCompiler/lib/Driver/Driver.cpp | 7 + + IGC/VectorCompiler/lib/GenXCodeGen/GenX.td | 361 +++++++++++------- + .../lib/GenXCodeGen/GenXCisaBuilder.cpp | 47 +-- + .../lib/GenXCodeGen/GenXLowering.cpp | 2 +- + .../lib/GenXCodeGen/GenXRegionUtils.cpp | 15 +- + .../lib/GenXCodeGen/GenXSubtarget.cpp | 35 +- + .../lib/GenXCodeGen/GenXSubtarget.h | 232 +++++------ + .../lib/GenXCodeGen/GenXUtil.cpp | 2 +- + IGC/VectorCompiler/utils/vcb/vcb.cpp | 4 +- + 11 files changed, 414 insertions(+), 373 deletions(-) + +diff --git a/IGC/VectorCompiler/cmake/supported_platforms_list.cmake b/IGC/VectorCompiler/cmake/supported_platforms_list.cmake +index 7f40ef08a..910df2e97 100644 +--- a/IGC/VectorCompiler/cmake/supported_platforms_list.cmake ++++ b/IGC/VectorCompiler/cmake/supported_platforms_list.cmake +@@ -1,21 +1,19 @@ ++#=========================== begin_copyright_notice ============================ ++# ++# Copyright (C) 2020-2022 Intel Corporation ++# ++# SPDX-License-Identifier: MIT ++# ++#============================ end_copyright_notice ============================= + + set(SUPPORTED_VC_PLATFORMS +- "BDW" +- "SKL" +- "BXT" +- "KBL" +- "GLK" +- "ICLLP" +- "TGLLP" +- "RKL" +- "DG1" +- "XEHP" +- "ADLP" +- "ADLS" +- "ADLN" +- "DG2" +- "PVC" +- "PVCXT_A0" +- "PVCXT" +- "MTL" ++ "Gen8" ++ "Gen9" ++ "Gen9LP" ++ "Gen11" ++ "XeLP" ++ "XeHP" ++ "XeHPG" ++ "XeLPG" ++ "XeHPC" + ) +diff --git a/IGC/VectorCompiler/igcdeps/src/TranslationInterface.cpp b/IGC/VectorCompiler/igcdeps/src/TranslationInterface.cpp +index c39577dee..221111b02 100644 +--- a/IGC/VectorCompiler/igcdeps/src/TranslationInterface.cpp ++++ b/IGC/VectorCompiler/igcdeps/src/TranslationInterface.cpp +@@ -142,14 +142,52 @@ std::unique_ptr getVCModuleBuffer() { + false /* RequiresNullTerminator */); + } + ++static std::pair ++getPlatformName(const PLATFORM &Platform) { ++ constexpr unsigned ComputeTileMaskPVC = 7; ++ auto Core = Platform.eRenderCoreFamily; ++ auto Product = Platform.eProductFamily; ++ unsigned DevId = Platform.usDeviceID; ++ unsigned RevId = Platform.usRevId; ++ ++ switch (Core) { ++ case IGFX_GEN8_CORE: ++ return {"Gen8", RevId}; ++ case IGFX_GEN9_CORE: ++ if (Product == IGFX_BROXTON || Product == IGFX_GEMINILAKE) ++ return {"Gen9LP", RevId}; ++ return {"Gen9", RevId}; ++ case IGFX_GEN11_CORE: ++ case IGFX_GEN11LP_CORE: ++ return {"Gen11", RevId}; ++ case IGFX_GEN12_CORE: ++ case IGFX_GEN12LP_CORE: ++ return {"XeLP", RevId}; ++ case IGFX_XE_HP_CORE: ++ return {"XeHP", RevId}; ++ case IGFX_XE_HPG_CORE: ++ if (Product == IGFX_DG2) ++ return {"XeHPG", RevId}; ++ if (Product == IGFX_METEORLAKE) ++ return {"XeLPG", RevId}; ++ break; ++ case IGFX_XE_HPC_CORE: ++ if (Product == IGFX_PVC) ++ return {"XeHPC", RevId & ComputeTileMaskPVC}; ++ break; ++ default: ++ break; ++ } ++ IGC_ASSERT_EXIT_MESSAGE(0, "Unsupported platform"); ++ return {"Invalid", -1}; ++} ++ + static void adjustPlatform(const IGC::CPlatform &IGCPlatform, + vc::CompileOptions &Opts) { + auto &PlatformInfo = IGCPlatform.getPlatformInfo(); +- unsigned RevId = PlatformInfo.usRevId; +- const char *PlatformStr = +- cmc::getPlatformStr(PlatformInfo, /* inout */ RevId); +- Opts.CPUStr = PlatformStr ? PlatformStr : ""; +- Opts.RevId = RevId; ++ ++ std::tie(Opts.CPUStr, Opts.RevId) = getPlatformName(PlatformInfo); ++ + Opts.HasL1ReadOnlyCache = IGCPlatform.hasL1ReadOnlyCache(); + Opts.HasLocalMemFenceSupress = IGCPlatform.localMemFenceSupress(); + Opts.HasMultiTile = IGCPlatform.hasMultiTile(); +diff --git a/IGC/VectorCompiler/lib/Driver/Driver.cpp b/IGC/VectorCompiler/lib/Driver/Driver.cpp +index cab266047..5a4efaea0 100644 +--- a/IGC/VectorCompiler/lib/Driver/Driver.cpp ++++ b/IGC/VectorCompiler/lib/Driver/Driver.cpp +@@ -175,6 +175,13 @@ static std::string getSubtargetFeatureString(const vc::CompileOptions &Opts) { + if (Opts.HasHalfSIMDLSC) + Features.AddFeature("feature_has_half_simd_lsc"); + ++ if (Opts.CPUStr == "XeHPC") { ++ if (Opts.RevId < 3) ++ Features.AddFeature("lightweight_i64_emulation", false); ++ else if (Opts.RevId < 5) ++ Features.AddFeature("add64", false); ++ } ++ + return Features.getString(); + } + +diff --git a/IGC/VectorCompiler/lib/GenXCodeGen/GenX.td b/IGC/VectorCompiler/lib/GenXCodeGen/GenX.td +index 3633657fa..cafa7e86b 100644 +--- a/IGC/VectorCompiler/lib/GenXCodeGen/GenX.td ++++ b/IGC/VectorCompiler/lib/GenXCodeGen/GenX.td +@@ -149,6 +149,14 @@ def FeatureHasLSC : SubtargetFeature<"feature_has_lsc", + "true", + "Target supports LSC messages">; + ++def FeatureHasAdd3 : SubtargetFeature<"feature_has_add3", ++ "HasAdd3", "true", ++ "Target supports 3-way addition">; ++ ++def FeatureHasBfn : SubtargetFeature<"feature_has_bfn", ++ "HasBfn", "true", ++ "Target supports 3-way boolean function">; ++ + def FeatureHasHalfSIMDLSC : SubtargetFeature<"feature_has_half_simd_lsc", + "HasHalfSIMDLSC", + "true", +@@ -165,6 +173,47 @@ def FeatureMultiIndirectByteRegioning : SubtargetFeature<"multi_indirect_byte_re + "true", + "Vx1 and VxH indirect addressing for Byte datatypes">; + ++def FeatureWaNoA32ByteScatter : SubtargetFeature<"wa_no_a32_byte_scatter_stateless", ++ "HasWaNoA32ByteScatter", "true", ++ "Target doesn't support A32 byte scatter stateless message">; ++ ++def FeatureIndirectGRFCrossing : SubtargetFeature<"indirect_grf_crossing", ++ "HasIndirectGRFCrossing", "true", ++ "Target supports an indirect region crossing one GRF boundary">; ++ ++def FeatureIndirectByteGRFCrossing : SubtargetFeature<"indirect_byte_grf_crossing", ++ "HasIndirectGRFCrossing", "true", ++ "Target supports an indirect region crossing one GRF boundary">; ++ ++def FeatureSLM64K : SubtargetFeature<"slm_64k", ++ "MaxSLMSize", "64", ++ "Target supports up to 64k of SLM">; ++ ++def FeatureSLM128K : SubtargetFeature<"slm_128k", ++ "MaxSLMSize", "128", ++ "Target supports up to 128k of SLM">; ++ ++ ++def FeatureHasSad2 : SubtargetFeature<"feature_has_sad2", ++ "HasSad2", "true", ++ "Target supports sad2/sad2a instructions">; ++ ++def FeatureHasOWordSLM : SubtargetFeature<"feature_has_slm_oword", ++ "HasSLMOWord", "true", ++ "Target supports OWord block SLM messages">; ++ ++def FeatureHasMadSimd32 : SubtargetFeature<"feature_has_mad_simd32", ++ "HasMadSimd32", "true", ++ "Target supports SIMD32 mad instruction">; ++ ++def FeatureHasNamedBarriers : SubtargetFeature<"feature_has_named_barriers", ++ "HasNamedBarriers", "true", ++ "Target supports named barriers">; ++ ++def FeatureHasMediaWalker : SubtargetFeature<"feature_has_media_walker", ++ "HasMediaWalker", "true", ++ "Target supports media walker interface">; ++ + //===----------------------------------------------------------------------===// + // GenX processors supported. + //===----------------------------------------------------------------------===// +@@ -172,152 +221,172 @@ def FeatureMultiIndirectByteRegioning : SubtargetFeature<"multi_indirect_byte_re + class Proc Features> + : Processor; + +-def : Proc<"generic", []>; +-def : Proc<"BDW", [FeatureLongLong, FeatureSwitchjmp, +- FeatureIntDivRem32, +- FeatureInstrAdd64, +- FeatureFP64, +- FeatureIEEEDivSqrt, +- FeatureHasPackedFloat, +- FeatureMultiIndirectByteRegioning, +- FeatureHWTIDFromPredef]>; +-def : Proc<"SKL", [FeatureLongLong, FeatureSwitchjmp, +- FeatureIntDivRem32, +- FeatureUseMulDDQ, +- FeatureInstrAdd64, +- FeatureFP64, +- FeatureIEEEDivSqrt, +- FeatureHasPackedFloat, +- FeatureHWTIDFromPredef, +- FeatureMultiIndirectByteRegioning, +- FeaturePreemption]>; +-def : Proc<"BXT", [FeatureLongLong, FeatureSwitchjmp, +- FeatureIntDivRem32, +- FeatureUseMulDDQ, +- FeatureInstrAdd64, +- FeatureFP64, +- FeatureHasPackedFloat, +- FeatureHWTIDFromPredef, +- FeatureMultiIndirectByteRegioning, +- FeaturePreemption]>; +-def : Proc<"KBL", [FeatureLongLong, FeatureSwitchjmp, +- FeatureIntDivRem32, +- FeatureUseMulDDQ, +- FeatureInstrAdd64, +- FeatureFP64, +- FeatureIEEEDivSqrt, +- FeatureHasPackedFloat, +- FeatureHWTIDFromPredef, +- FeatureMultiIndirectByteRegioning, +- FeaturePreemption]>; +-def : Proc<"GLK", [FeatureLongLong, FeatureSwitchjmp, +- FeatureIntDivRem32, +- FeatureUseMulDDQ, +- FeatureInstrAdd64, +- FeatureFP64, +- FeatureHasPackedFloat, +- FeatureHWTIDFromPredef, +- FeatureMultiIndirectByteRegioning, +- FeaturePreemption]>; +-def : Proc<"ICLLP", [FeatureLongLongEmulation, FeatureSwitchjmp, +- FeatureIntDivRem32, FeatureInstrBitRotate, +- FeatureIEEEDivSqrt, +- FeatureHWTIDFromPredef, +- FeatureHasPackedFloat, +- FeatureMultiIndirectByteRegioning, +- FeaturePreemption]>; +-def : Proc<"TGLLP", [FeatureLongLongEmulation, FeatureIntDivRem32, +- FeatureInstrBitRotate, FeatureWAFusedEUNoMask, +- FeatureHWTIDFromPredef, +- FeatureHasPackedFloat, +- FeatureMultiIndirectByteRegioning, +- FeaturePreemption, FeatureFusedEU]>; +-def : Proc<"RKL", [FeatureLongLongEmulation, FeatureIntDivRem32, +- FeatureInstrBitRotate, FeatureWAFusedEUNoMask, +- FeatureHWTIDFromPredef, +- FeatureHasPackedFloat, +- FeatureMultiIndirectByteRegioning, +- FeaturePreemption, FeatureFusedEU]>; +-def : Proc<"DG1", [FeatureLongLongEmulation, FeatureIntDivRem32, +- FeatureInstrBitRotate, FeatureWAFusedEUNoMask, +- FeatureHWTIDFromPredef, +- FeatureHasPackedFloat, +- FeatureMultiIndirectByteRegioning, +- FeaturePreemption, FeatureFusedEU]>; +-def : Proc<"XEHP", [FeatureLongLong, +- FeatureInstrAdd64, +- FeatureFP64, +- FeatureIEEEDivSqrt, +- FeatureThreadPayloadInMemory, +- FeatureHasPackedFloat, +- FeatureMultiIndirectByteRegioning, +- FeatureInstrBitRotate, FeatureFusedEU]>; +-def : Proc<"ADLS", [FeatureLongLongEmulation, FeatureIntDivRem32, +- FeatureInstrBitRotate, FeatureWAFusedEUNoMask, +- FeatureHasPackedFloat, +- FeatureHWTIDFromPredef, +- FeatureMultiIndirectByteRegioning, +- FeaturePreemption, FeatureFusedEU]>; +-def : Proc<"ADLP", [FeatureLongLongEmulation, FeatureIntDivRem32, +- FeatureInstrBitRotate, FeatureWAFusedEUNoMask, +- FeatureHasPackedFloat, +- FeatureHWTIDFromPredef, +- FeatureMultiIndirectByteRegioning, +- FeaturePreemption, FeatureFusedEU]>; +-def : Proc<"ADLN", [FeatureLongLongEmulation, FeatureIntDivRem32, +- FeatureInstrBitRotate, FeatureWAFusedEUNoMask, +- FeatureHasPackedFloat, +- FeatureHWTIDFromPredef, +- FeatureMultiIndirectByteRegioning, +- FeaturePreemption, FeatureFusedEU]>; +-def : Proc<"DG2", [FeatureLongLongEmulation, +- FeatureThreadPayloadInMemory, +- FeatureHasPackedFloat, +- FeatureInstrBitRotate, +- FeatureMultiIndirectByteRegioning, +- FeatureHasLSC, FeatureFusedEU]>; +-def : Proc<"PVC", [FeatureLongLong, FeatureGRFByteSize64, +- FeatureLSCMaxWidth32, +- FeatureSwitchjmp, +- FeatureFP64, +- FeatureIEEEDivSqrt, +- FeatureThreadPayloadInMemory, +- FeatureHasPackedFloat, +- FeatureInstr64BitRotate, +- FeatureBfMixedModeWidth16, +- FeatureHasLSC]>; +-def : Proc<"PVCXT_A0", [FeatureLongLong, FeatureGRFByteSize64, +- FeatureLSCMaxWidth32, +- FeaturePartialI64Emulation, +- FeatureSwitchjmp, +- FeatureFP64, +- FeatureIEEEDivSqrt, +- FeatureHasPackedFloat, +- FeatureThreadPayloadInMemory, +- FeatureInstr64BitRotate, +- FeatureBfMixedModeWidth16, +- FeatureHasLSC]>; +-def : Proc<"PVCXT", [FeatureLongLong, FeatureGRFByteSize64, +- FeatureLSCMaxWidth32, +- FeaturePartialI64Emulation, +- FeatureSwitchjmp, +- FeatureInstrAdd64, +- FeatureFP64, +- FeatureIEEEDivSqrt, +- FeatureHasPackedFloat, +- FeatureThreadPayloadInMemory, +- FeatureInstr64BitRotate, +- FeatureBfMixedModeWidth16, +- FeatureHasLSC]>; +-def : Proc<"MTL", [FeatureLongLongEmulation, +- FeatureFP64, +- FeatureFDivFSqrt64Emulation, +- FeatureHasPackedFloat, +- FeatureThreadPayloadInMemory, +- FeatureInstrBitRotate, +- FeatureBfMixedModeWidth16, +- FeatureMultiIndirectByteRegioning, +- FeatureHasLSC, FeatureFusedEU]>; ++def : Proc<"generic", []>; ++ ++def : Proc<"Gen8", [ ++ FeatureFP64, ++ FeatureHWTIDFromPredef, ++ FeatureHasMediaWalker, ++ FeatureHasPackedFloat, ++ FeatureHasSad2, ++ FeatureIEEEDivSqrt, ++ FeatureInstrAdd64, ++ FeatureIntDivRem32, ++ FeatureLongLong, ++ FeatureMultiIndirectByteRegioning, ++ FeatureSLM64K, ++ FeatureSwitchjmp, ++ FeatureWaNoA32ByteScatter, ++]>; ++ ++def : Proc<"Gen9", [ ++ FeatureFP64, ++ FeatureHWTIDFromPredef, ++ FeatureHasMediaWalker, ++ FeatureHasPackedFloat, ++ FeatureHasSad2, ++ FeatureIEEEDivSqrt, ++ FeatureIndirectByteGRFCrossing, ++ FeatureIndirectGRFCrossing, ++ FeatureInstrAdd64, ++ FeatureIntDivRem32, ++ FeatureLongLong, ++ FeatureMultiIndirectByteRegioning, ++ FeaturePreemption, ++ FeatureSLM64K, ++ FeatureSwitchjmp, ++ FeatureUseMulDDQ, ++ FeatureWaNoA32ByteScatter, ++]>; ++ ++def : Proc<"Gen9LP", [ ++ FeatureFP64, ++ FeatureHWTIDFromPredef, ++ FeatureHasMediaWalker, ++ FeatureHasPackedFloat, ++ FeatureHasSad2, ++ FeatureIndirectByteGRFCrossing, ++ FeatureIndirectGRFCrossing, ++ FeatureInstrAdd64, ++ FeatureIntDivRem32, ++ FeatureLongLong, ++ FeatureMultiIndirectByteRegioning, ++ FeaturePreemption, ++ FeatureSLM64K, ++ FeatureSwitchjmp, ++ FeatureUseMulDDQ, ++ FeatureWaNoA32ByteScatter, ++]>; ++ ++ ++def : Proc<"Gen11", [ ++ FeatureHWTIDFromPredef, ++ FeatureHasMediaWalker, ++ FeatureHasOWordSLM, ++ FeatureHasPackedFloat, ++ FeatureIEEEDivSqrt, ++ FeatureIndirectByteGRFCrossing, ++ FeatureIndirectGRFCrossing, ++ FeatureInstrBitRotate, ++ FeatureIntDivRem32, ++ FeatureLongLongEmulation, ++ FeatureMultiIndirectByteRegioning, ++ FeaturePreemption, ++ FeatureSLM64K, ++ FeatureSwitchjmp, ++]>; ++ ++def : Proc<"XeLP", [ ++ FeatureFusedEU, ++ FeatureHWTIDFromPredef, ++ FeatureHasMediaWalker, ++ FeatureHasOWordSLM, ++ FeatureHasPackedFloat, ++ FeatureIndirectByteGRFCrossing, ++ FeatureIndirectGRFCrossing, ++ FeatureInstrBitRotate, ++ FeatureIntDivRem32, ++ FeatureLongLongEmulation, ++ FeatureMultiIndirectByteRegioning, ++ FeaturePreemption, ++ FeatureSLM64K, ++ FeatureWAFusedEUNoMask, ++]>; ++ ++def : Proc<"XeHP", [ ++ FeatureFP64, ++ FeatureFusedEU, ++ FeatureHasAdd3, ++ FeatureHasBfn, ++ FeatureHasOWordSLM, ++ FeatureHasPackedFloat, ++ FeatureIEEEDivSqrt, ++ FeatureIndirectByteGRFCrossing, ++ FeatureIndirectGRFCrossing, ++ FeatureInstrAdd64, ++ FeatureInstrBitRotate, ++ FeatureLongLong, ++ FeatureMultiIndirectByteRegioning, ++ FeatureSLM128K, ++ FeatureThreadPayloadInMemory, ++]>; ++ ++def : Proc<"XeHPG", [ ++ FeatureFusedEU, ++ FeatureHasAdd3, ++ FeatureHasBfn, ++ FeatureHasLSC, ++ FeatureHasOWordSLM, ++ FeatureHasPackedFloat, ++ FeatureIndirectByteGRFCrossing, ++ FeatureIndirectGRFCrossing, ++ FeatureInstrBitRotate, ++ FeatureLongLongEmulation, ++ FeatureMultiIndirectByteRegioning, ++ FeatureSLM128K, ++ FeatureThreadPayloadInMemory, ++]>; ++ ++def : Proc<"XeLPG", [ ++ FeatureBfMixedModeWidth16, ++ FeatureFDivFSqrt64Emulation, ++ FeatureFP64, ++ FeatureFusedEU, ++ FeatureHasAdd3, ++ FeatureHasBfn, ++ FeatureHasLSC, ++ FeatureHasOWordSLM, ++ FeatureHasPackedFloat, ++ FeatureIndirectByteGRFCrossing, ++ FeatureIndirectGRFCrossing, ++ FeatureInstrBitRotate, ++ FeatureLongLongEmulation, ++ FeatureMultiIndirectByteRegioning, ++ FeatureSLM128K, ++ FeatureThreadPayloadInMemory, ++]>; ++ ++def : Proc<"XeHPC", [ ++ FeatureBfMixedModeWidth16, ++ FeatureFP64, ++ FeatureGRFByteSize64, ++ FeatureHasAdd3, ++ FeatureHasBfn, ++ FeatureHasLSC, ++ FeatureHasNamedBarriers, ++ FeatureHasOWordSLM, ++ FeatureHasPackedFloat, ++ FeatureIEEEDivSqrt, ++ FeatureIndirectGRFCrossing, ++ FeatureInstr64BitRotate, ++ FeatureInstrAdd64, ++ FeatureLSCMaxWidth32, ++ FeatureLongLong, ++ FeaturePartialI64Emulation, ++ FeatureSLM128K, ++ FeatureSwitchjmp, ++ FeatureThreadPayloadInMemory, ++]>; + + def GenX : Target { + // Nothing here (yet?) +diff --git a/IGC/VectorCompiler/lib/GenXCodeGen/GenXCisaBuilder.cpp b/IGC/VectorCompiler/lib/GenXCodeGen/GenXCisaBuilder.cpp +index 3a772e372..184c8d735 100644 +--- a/IGC/VectorCompiler/lib/GenXCodeGen/GenXCisaBuilder.cpp ++++ b/IGC/VectorCompiler/lib/GenXCodeGen/GenXCisaBuilder.cpp +@@ -5669,7 +5669,27 @@ void GenXKernelBuilder::buildGetHWID(CallInst *CI, const DstOpndDesc &DstDesc) { + ISA_MOV, nullptr, false, vISA_EMASK_M1_NM, EXEC_SIZE_1, dst, src)); + }; + +- if (Subtarget->isPVC()) { ++ switch (Subtarget->getTargetId()) { ++ case GenXSubtarget::XeHP: ++ case GenXSubtarget::XeHPG: ++ case GenXSubtarget::XeLPG: ++ // [13:11] Slice ID. ++ // [10:9] Dual - SubSlice ID ++ // [8] SubSlice ID. ++ // [7] : EUID[2] ++ // [6] : Reserved ++ // [5:4] EUID[1:0] ++ // [3] : Reserved MBZ ++ // [2:0] : TID ++ // ++ // HWTID is calculated using a concatenation of TID:EUID:SubSliceID:SliceID ++ ++ // Load sr0 with [13:0] mask ++ loadMaskedSR0(14); ++ // Remove reserved bits ++ removeBitRange(6, 1); ++ break; ++ case GenXSubtarget::XeHPC: + // [14:12] Slice ID. + // [11:9] SubSlice ID + // [8] : EUID[2] +@@ -5682,33 +5702,14 @@ void GenXKernelBuilder::buildGetHWID(CallInst *CI, const DstOpndDesc &DstDesc) { + + // Load sr0 with [14:0] mask + loadMaskedSR0(15); +- + // Remove reserved bits + removeBitRange(6, 2); +- removeBitRange(3, 1); +- +- // Store final value +- writeHwtidToDst(); +- +- return; ++ break; ++ default: ++ IGC_ASSERT_EXIT_MESSAGE(0, "The platform does not support HWTID"); + } +- // XeHP_SDV +- // [13:11] Slice ID. +- // [10:9] Dual - SubSlice ID +- // [8] SubSlice ID. +- // [7] : EUID[2] +- // [6] : Reserved +- // [5:4] EUID[1:0] +- // [3] : Reserved MBZ +- // [2:0] : TID +- // +- // HWTID is calculated using a concatenation of TID:EUID:SubSliceID:SliceID +- +- // Load sr0 with [13:0] mask +- loadMaskedSR0(14); + + // Remove reserved bits +- removeBitRange(6, 1); + removeBitRange(3, 1); + + // Store final value +diff --git a/IGC/VectorCompiler/lib/GenXCodeGen/GenXLowering.cpp b/IGC/VectorCompiler/lib/GenXCodeGen/GenXLowering.cpp +index 9fd7e4145..654c1baa4 100644 +--- a/IGC/VectorCompiler/lib/GenXCodeGen/GenXLowering.cpp ++++ b/IGC/VectorCompiler/lib/GenXCodeGen/GenXLowering.cpp +@@ -3236,7 +3236,7 @@ bool GenXLowering::processInst(Instruction *Inst) { + if (ST) { + // use gather/scatter to implement SLM oword load/store on + // legacy platforms +- if (!ST->isICLLPplus()) { ++ if (!ST->hasSLMOWord()) { + if (translateSLMOWord(CI, IntrinsicID)) + return true; + } +diff --git a/IGC/VectorCompiler/lib/GenXCodeGen/GenXRegionUtils.cpp b/IGC/VectorCompiler/lib/GenXCodeGen/GenXRegionUtils.cpp +index 5ceb0673b..50eef51d8 100644 +--- a/IGC/VectorCompiler/lib/GenXCodeGen/GenXRegionUtils.cpp ++++ b/IGC/VectorCompiler/lib/GenXCodeGen/GenXRegionUtils.cpp +@@ -1,6 +1,6 @@ + /*========================== begin_copyright_notice ============================ + +-Copyright (C) 2017-2021 Intel Corporation ++Copyright (C) 2017-2022 Intel Corporation + + SPDX-License-Identifier: MIT + +@@ -389,7 +389,8 @@ unsigned genx::getLegalRegionSizeForTarget(const GenXSubtarget &ST, + // boundary. + unsigned NumGRF = 2; + // For PVC it's legal to read only from one GFR in byte source +- if (ST.isPVC() && R.ElementBytes == genx::ByteBytes) ++ if (!ST.hasMultiIndirectByteRegioning() && ++ R.ElementBytes == genx::ByteBytes) + NumGRF = 1; + ElementsToBoundary = (NumGRF * ElementsPerGRF) - + ((RealIdx + OffsetElements) % ElementsPerGRF); +@@ -527,11 +528,11 @@ unsigned genx::getLegalRegionSizeForTarget(const GenXSubtarget &ST, + + } + } +- if (AdjustValidWidthForTarget) +- if (ST.isPVC() && R.is2D()) { +- while ((ValidWidth * R.ElementBytes) >= 64) +- ValidWidth /= 2; +- } ++ if (AdjustValidWidthForTarget && !ST.hasMultiIndirectByteRegioning() && ++ R.is2D()) { ++ while ((ValidWidth * R.ElementBytes) >= ST.getGRFByteSize()) ++ ValidWidth /= 2; ++ } + + // Some targets do not have multi indirect byte regioning and in general case + // transformation from multi indirect region to indirect is possible for +diff --git a/IGC/VectorCompiler/lib/GenXCodeGen/GenXSubtarget.cpp b/IGC/VectorCompiler/lib/GenXCodeGen/GenXSubtarget.cpp +index afe25ff7f..3385e9da2 100644 +--- a/IGC/VectorCompiler/lib/GenXCodeGen/GenXSubtarget.cpp ++++ b/IGC/VectorCompiler/lib/GenXCodeGen/GenXSubtarget.cpp +@@ -52,30 +52,20 @@ void GenXSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { + else + StackSurf = PreDefined_Surface::PREDEFINED_SURFACE_STACK; + +- GenXVariant = llvm::StringSwitch(CPU) +- .Case("generic", GENERIC_ARCH) +- .Case("BDW", GENX_BDW) +- .Case("SKL", GENX_SKL) +- .Case("BXT", GENX_BXT) +- .Case("KBL", GENX_KBL) +- .Case("GLK", GENX_GLK) +- .Case("ICLLP", GENX_ICLLP) +- .Case("TGLLP", GENX_TGLLP) +- .Case("RKL", GENX_RKL) +- .Case("DG1", GENX_DG1) +- .Case("ADLS", GENX_ADLS) +- .Case("ADLP", GENX_ADLP) +- .Case("ADLN", GENX_ADLN) +- .Cases("XEHP", "XEHP_SDV", XE_HP_SDV) +- .Case("DG2", XE_DG2) +- .Case("MTL", XE_MTL) +- .Case("PVC", XE_PVC) +- .Case("PVCXT_A0", XE_PVCXT_A0) +- .Case("PVCXT", XE_PVCXT) +- .Default(UNDEFINED_ARCH); ++ TargetId = llvm::StringSwitch(CPU) ++ .Case("Gen8", Gen8) ++ .Case("Gen9", Gen9) ++ .Case("Gen9LP", Gen9LP) ++ .Case("Gen11", Gen11) ++ .Case("XeLP", XeLP) ++ .Case("XeHP", XeHP) ++ .Case("XeHPG", XeHPG) ++ .Case("XeLPG", XeLPG) ++ .Case("XeHPC", XeHPC) ++ .Default(Invalid); + + std::string CPUName(CPU); +- if (CPUName.empty() || GenXVariant == UNDEFINED_ARCH) ++ if (CPUName.empty() || TargetId == Invalid) + report_fatal_error("Undefined or blank arch passed"); + + ParseSubtargetFeatures(CPUName, +@@ -97,6 +87,5 @@ GenXSubtarget::GenXSubtarget(const Triple &TT, const std::string &CPU, + #endif + FS), + TargetTriple(TT) { +- + initSubtargetFeatures(CPU, FS); + } +diff --git a/IGC/VectorCompiler/lib/GenXCodeGen/GenXSubtarget.h b/IGC/VectorCompiler/lib/GenXCodeGen/GenXSubtarget.h +index 121b4d0a5..ba8b43c7d 100644 +--- a/IGC/VectorCompiler/lib/GenXCodeGen/GenXSubtarget.h ++++ b/IGC/VectorCompiler/lib/GenXCodeGen/GenXSubtarget.h +@@ -45,36 +45,25 @@ class StringRef; + class TargetMachine; + + class GenXSubtarget final : public GenXGenSubtargetInfo { ++public: ++ enum GenXTargetId { ++ Gen8, ++ Gen9, ++ Gen9LP, ++ Gen11, ++ XeLP, ++ XeHP, ++ XeHPG, ++ XeLPG, ++ XeHPC, ++ Invalid, ++ }; + + protected: + // TargetTriple - What processor and OS we're targeting. + Triple TargetTriple; + +- enum GenXTag { +- UNDEFINED_ARCH, +- GENERIC_ARCH, +- GENX_BDW, +- GENX_SKL, +- GENX_BXT, +- GENX_KBL, +- GENX_GLK, +- GENX_ICLLP, +- GENX_TGLLP, +- GENX_RKL, +- GENX_DG1, +- GENX_ADLS, +- GENX_ADLP, +- GENX_ADLN, +- XE_HP_SDV, +- XE_MTL, +- XE_DG2, +- XE_PVC, +- XE_PVCXT_A0, +- XE_PVCXT, +- }; +- +- // GenXVariant - GenX Tag identifying the variant to compile for +- GenXTag GenXVariant; ++ GenXTargetId TargetId; + + private: + // HasLongLong - True if subtarget supports long long type +@@ -170,18 +159,51 @@ private: + /// True if subtarget supports half SIMD LSC messages + bool HasHalfSIMDLSC = false; + +- // Has multi-tile. ++ /// Has multi-tile. + bool HasMultiTile = false; + +- // Has L3 cache-coherent cross tiles. ++ /// Has L3 cache-coherent cross tiles. + bool HasL3CacheCoherentCrossTiles = false; + +- // Has L3 flush on GPU-scope invalidate. ++ /// Has L3 flush on GPU-scope invalidate. + bool HasL3FlushOnGPUScopeInvalidate = false; + +- // True if Vx1 and VxH indirect addressing are allowed for Byte datatypes ++ /// True if Vx1 and VxH indirect addressing are allowed for Byte datatypes + bool HasMultiIndirectByteRegioning = false; + ++ /// True if subtarget supports ADD3 instruction ++ bool HasAdd3 = false; ++ ++ /// True if subtarget supports BFN instruction ++ bool HasBfn = false; ++ ++ /// True if subtarget supports SAD and SADA2 instructions ++ bool HasSad2 = false; ++ ++ /// True if subtarget supports OWord SLM read/write messages ++ bool HasSLMOWord = false; ++ ++ /// True if subtarget supports SIMD32 MAD instruction ++ bool HasMadSimd32 = false; ++ ++ /// True if subtarget requires A32 byte scatter emulation ++ bool HasWaNoA32ByteScatter = false; ++ ++ /// True if subtarget supports indirect cross-grf access ++ bool HasIndirectGRFCrossing = false; ++ ++ /// True if subtarget supports indirect cross-grf byte access ++ bool HasIndirectByteGRFCrossing = false; ++ ++ /// True if subtarget supports named barriers ++ bool HasNamedBarriers = false; ++ ++ /// True if subtarget supports media walker ++ bool HasMediaWalker = false; ++ ++ /// Max supported SLM size (in kbytes) ++ int MaxSLMSize = 64; ++ + // Shows which surface should we use for stack + PreDefined_Surface StackSurf; + +@@ -192,6 +214,8 @@ public: + GenXSubtarget(const Triple &TT, const std::string &CPU, + const std::string &FS); + ++ GenXTargetId getTargetId() const { return TargetId; } ++ + // GRF size in bytes. + unsigned getGRFByteSize() const { return GRFByteSize; } + +@@ -224,85 +248,22 @@ public: + void initSubtargetFeatures(StringRef CPU, StringRef FS); + + public: +- +- /// * isBDW - true if target is BDW +- bool isBDW() const { return GenXVariant == GENX_BDW; } +- +- /// * isBDWplus - true if target is BDW or later +- bool isBDWplus() const { return GenXVariant >= GENX_BDW; } +- +- /// * isSKL - true if target is SKL +- bool isSKL() const { return GenXVariant == GENX_SKL; } +- +- /// * isSKLplus - true if target is SKL or later +- bool isSKLplus() const { return GenXVariant >= GENX_SKL; } +- +- /// * isBXT - true if target is BXT +- bool isBXT() const { return GenXVariant == GENX_BXT; } +- +- /// * isKBL - true if target is KBL +- bool isKBL() const { return GenXVariant == GENX_KBL; } +- +- /// * isGLK - true if target is GLK +- bool isGLK() const { return GenXVariant == GENX_GLK; } +- +- /// * isICLLPplus - true if target is ICLLP or later +- bool isICLLPplus() const { return GenXVariant >= GENX_ICLLP; } +- +- /// * isICLLP - true if target is ICL LP +- bool isICLLP() const { return GenXVariant == GENX_ICLLP; } +- /// * isTGLLP - true if target is TGL LP +- bool isTGLLP() const { return GenXVariant == GENX_TGLLP; } +- /// * isRKL - true if target is RKL +- bool isRKL() const { return GenXVariant == GENX_RKL; } +- /// * isDG1 - true if target is DG1 +- bool isDG1() const { return GenXVariant == GENX_DG1; } +- /// * isXEHP - true if target is XEHP +- bool isXEHP() const { +- return GenXVariant == XE_HP_SDV; +- } +- /// * isADLS - true if target is ADLS +- bool isADLS() const { return GenXVariant == GENX_ADLS; } +- /// * isADLP - true if target is ADLP +- bool isADLP() const { return GenXVariant == GENX_ADLP; } +- /// * isADLN - true if target is ADLN +- bool isADLN() const { return GenXVariant == GENX_ADLN; } +- /// * isMTL - true if target is MTL +- bool isMTL() const { return GenXVariant == XE_MTL; } + /// * translateMediaWalker - true if translate media walker APIs +- bool translateMediaWalker() const { return GenXVariant >= XE_HP_SDV; } ++ bool translateMediaWalker() const { return !HasMediaWalker; } ++ + // TODO: consider implementing 2 different getters + /// * has add3 and bfn instructions +- bool hasAdd3Bfn() const { return GenXVariant >= XE_HP_SDV; } +- int dpasWidth() const { +- if (isPVC()) +- return 16; +- return 8; +- } ++ bool hasAdd3Bfn() const { return HasAdd3 && HasBfn; } ++ ++ int dpasWidth() const { return GRFByteSize / 4; } ++ + unsigned bfMixedModeWidth() const { + if (HasBfMixedModeWidth16) + return 16; + return 8; + } +- /// * isDG2 - true if target is DG2 +- bool isDG2() const { return GenXVariant == XE_DG2; } +- /// * isPVC - true if target is PVC +- bool isPVC() const { return isPVCXL() || isPVCXT_A0() || isPVCXT(); } +- +- /// * isPVCXT - true if target is PVCXT +- bool isPVCXT() const { return GenXVariant == XE_PVCXT; } + +- /// * isPVCXT_A0 - true if target is PVCXT_A0 +- bool isPVCXT_A0() const { return GenXVariant == XE_PVCXT_A0; } +- +- /// * isPVCXL - true if target is PVCXL +- bool isPVCXL() const { return GenXVariant == XE_PVC; } +- +- int getNumElementsInAddrReg() const { +- if (isPVC()) +- return 16; +- return 8; +- } ++ int getNumElementsInAddrReg() const { return GRFByteSize / 4; } + + bool translateLegacyMessages() const { + return (HasLSCMessages && TranslateLegacyMessages); +@@ -341,7 +302,9 @@ public: + + /// * WaNoA32ByteScatteredStatelessMessages - true if there is no A32 byte + /// scatter stateless message. +- bool WaNoA32ByteScatteredStatelessMessages() const { return !isICLLPplus(); } ++ bool WaNoA32ByteScatteredStatelessMessages() const { ++ return HasWaNoA32ByteScatter; ++ } + + /// * disableVectorDecomposition - true if vector decomposition is disabled. + bool disableVectorDecomposition() const { return DisableVectorDecomposition; } +@@ -370,13 +333,11 @@ public: + + /// * hasIndirectGRFCrossing - true if target supports an indirect region + /// crossing one GRF boundary +- bool hasIndirectGRFCrossing() const { return isSKLplus(); } ++ bool hasIndirectGRFCrossing() const { return HasIndirectGRFCrossing; } + + /// * hasIndirectByteGRFCrossing - true if target supports an indirect region + /// crossing one GRF boundary with byte type +- bool hasIndirectByteGRFCrossing() const { +- return hasIndirectGRFCrossing() && !isPVC(); +- } ++ bool hasIndirectByteGRFCrossing() const { return HasIndirectByteGRFCrossing; } + + /// * hasMultiIndirectByteRegioning - true if target supports an multi + /// indirect regions with byte type +@@ -384,29 +345,17 @@ public: + return HasMultiIndirectByteRegioning; + }; + +- bool hasNBarrier() const { return GenXVariant >= XE_PVC; } ++ bool hasNBarrier() const { return HasNamedBarriers; } + + /// * getMaxSlmSize - returns maximum allowed SLM size (in KB) + unsigned getMaxSlmSize() const { +- if (isXEHP() || isDG2() || isMTL() || isPVC()) +- return 128; +- return 64; ++ return MaxSLMSize; + } + + bool hasThreadPayloadInMemory() const { return HasThreadPayloadInMemory; } + + /// * hasSad2Support - returns true if sad2/sada2 are supported by target +- bool hasSad2Support() const { +- if (isICLLP() || isTGLLP()) +- return false; +- if (isDG1()) +- return false; +- if (isXEHP()) +- return false; +- if (isDG2() || isPVC()) +- return false; +- return true; +- } ++ bool hasSad2Support() const { return HasSad2; } + + bool hasBitRotate() const { return HasBitRotate; } + bool has64BitRotate() const { return Has64BitRotate; } +@@ -421,6 +370,10 @@ public: + return HasL3FlushOnGPUScopeInvalidate; + } + ++ bool hasSLMOWord() const { return HasSLMOWord; } ++ ++ bool hasMadSimd32() const { return HasMadSimd32; } ++ + /// * getsHWTIDFromPredef - some subtargets get HWTID from + // predefined variable instead of sr0, returns *true* for such ones. + bool getsHWTIDFromPredef() const { return GetsHWTIDFromPredef; } +@@ -429,42 +382,27 @@ public: + const Triple &getTargetTriple() const { return TargetTriple; } + + TARGET_PLATFORM getVisaPlatform() const { +- switch (GenXVariant) { +- case GENX_BDW: ++ switch (TargetId) { ++ case Gen8: + return TARGET_PLATFORM::GENX_BDW; +- case GENX_SKL: ++ case Gen9: + return TARGET_PLATFORM::GENX_SKL; +- case GENX_BXT: ++ case Gen9LP: + return TARGET_PLATFORM::GENX_BXT; +- case GENX_ICLLP: ++ case Gen11: + return TARGET_PLATFORM::GENX_ICLLP; +- case GENX_TGLLP: ++ case XeLP: + return TARGET_PLATFORM::GENX_TGLLP; +- case GENX_RKL: +- return TARGET_PLATFORM::GENX_TGLLP; +- case GENX_DG1: +- return TARGET_PLATFORM::GENX_TGLLP; +- case XE_HP_SDV: ++ case XeHP: + return TARGET_PLATFORM::Xe_XeHPSDV; +- case GENX_ADLS: +- return TARGET_PLATFORM::GENX_TGLLP; +- case GENX_ADLP: +- return TARGET_PLATFORM::GENX_TGLLP; +- case GENX_ADLN: +- return TARGET_PLATFORM::GENX_TGLLP; +- case XE_MTL: +- return TARGET_PLATFORM::Xe_MTL; +- case XE_DG2: ++ case XeHPG: + return TARGET_PLATFORM::Xe_DG2; +- case XE_PVC: +- return TARGET_PLATFORM::Xe_PVC; +- case XE_PVCXT_A0: +- case XE_PVCXT: ++ case XeLPG: ++ return TARGET_PLATFORM::Xe_MTL; ++ case XeHPC: ++ if (!partialI64Emulation()) ++ return TARGET_PLATFORM::Xe_PVC; + return TARGET_PLATFORM::Xe_PVCXT; +- case GENX_KBL: +- return TARGET_PLATFORM::GENX_SKL; +- case GENX_GLK: +- return TARGET_PLATFORM::GENX_BXT; + default: + return TARGET_PLATFORM::GENX_NONE; + } +diff --git a/IGC/VectorCompiler/lib/GenXCodeGen/GenXUtil.cpp b/IGC/VectorCompiler/lib/GenXCodeGen/GenXUtil.cpp +index cd9f80bc2..dc83f2743 100644 +--- a/IGC/VectorCompiler/lib/GenXCodeGen/GenXUtil.cpp ++++ b/IGC/VectorCompiler/lib/GenXCodeGen/GenXUtil.cpp +@@ -1963,7 +1963,7 @@ unsigned genx::getExecSizeAllowedBits(const Instruction *Inst, + case GenXIntrinsic::genx_uumad_sat: + case Intrinsic::fma: + // Do not emit simd32 mad for pre-ICLLP. +- return ST->isICLLPplus() ? 0x3f : 0x1f; ++ return ST->hasMadSimd32() ? 0x3f : 0x1f; + default: + return GenXIntrinsic::isGenXIntrinsic(ID) + ? GenXIntrinsicInfo(ID).getExecSizeAllowedBits() +diff --git a/IGC/VectorCompiler/utils/vcb/vcb.cpp b/IGC/VectorCompiler/utils/vcb/vcb.cpp +index 954aa15c7..f12dec2aa 100644 +--- a/IGC/VectorCompiler/utils/vcb/vcb.cpp ++++ b/IGC/VectorCompiler/utils/vcb/vcb.cpp +@@ -55,8 +55,8 @@ static cl::opt FeaturesStr("feature", + cl::init("+ocl_runtime")); + + static cl::opt +- PlatformString("cpu", cl::desc("platform for compilation (default: SKL)"), +- cl::value_desc("platform"), cl::init("SKL")); ++ PlatformString("cpu", cl::desc("platform for compilation (default: Gen9)"), ++ cl::value_desc("platform"), cl::init("Gen9")); + + static cl::opt OutputFilename("o", + cl::desc("Override output filename"), +-- +2.20.1 + diff -Nru intel-graphics-compiler-1.0.12504.6/debian/patches/fix-relative-includes.patch intel-graphics-compiler-1.0.12504.6/debian/patches/fix-relative-includes.patch --- intel-graphics-compiler-1.0.12504.6/debian/patches/fix-relative-includes.patch 2022-12-06 09:04:19.000000000 +0000 +++ intel-graphics-compiler-1.0.12504.6/debian/patches/fix-relative-includes.patch 1970-01-01 00:00:00.000000000 +0000 @@ -1,15 +0,0 @@ -Author: Andreas Beckmann -Description: fix relative #include paths -Bug: https://github.com/intel/intel-graphics-compiler/issues/260 - ---- a/IGC/AdaptorOCL/OCL/sp/sp_g8.cpp -+++ b/IGC/AdaptorOCL/OCL/sp/sp_g8.cpp -@@ -38,7 +38,7 @@ SPDX-License-Identifier: MIT - - #include "../../../Compiler/CodeGenPublic.h" - --#include "../../../visa/include/visaBuilder_interface.h" -+#include "../../../../visa/include/visaBuilder_interface.h" - - #include - #include diff -Nru intel-graphics-compiler-1.0.12504.6/debian/patches/fix-spirv-check.diff intel-graphics-compiler-1.0.12504.6/debian/patches/fix-spirv-check.diff --- intel-graphics-compiler-1.0.12504.6/debian/patches/fix-spirv-check.diff 2022-12-06 09:04:19.000000000 +0000 +++ intel-graphics-compiler-1.0.12504.6/debian/patches/fix-spirv-check.diff 1970-01-01 00:00:00.000000000 +0000 @@ -1,13 +0,0 @@ ---- a/external/SPIRV-Tools/CMakeLists.txt -+++ b/external/SPIRV-Tools/CMakeLists.txt -@@ -33,8 +33,8 @@ if(IGC_OPTION__SPIRV_TOOLS_MODE STREQUAL - set(IGC_BUILD__SPIRV-Tools_DIR "${SPIRV-Tools_ROOT_DIR}") - - set(INCLUDE_DIRS_LIST "${SPIRV-Tools_ROOT_DIR}/include" "${SPIRV-Headers_INCLUDE_DIR}") -- set_target_properties(SPIRV-Tools PROPERTIES INCLUDE_DIRECTORIES "${INCLUDE_DIRS_LIST}") -- set(IGC_BUILD__PROJ__SPIRV-Tools SPIRV-Tools) -+ set_target_properties(SPIRV-Tools-static PROPERTIES INCLUDE_DIRECTORIES "${INCLUDE_DIRS_LIST}") -+ set(IGC_BUILD__PROJ__SPIRV-Tools SPIRV-Tools-static) - - else() #By default use build from sources - message(STATUS "[SPIRV-Tools] : IGC_OPTION__SPIRV_TOOLS_MODE set to Source") diff -Nru intel-graphics-compiler-1.0.12504.6/debian/patches/series intel-graphics-compiler-1.0.12504.6/debian/patches/series --- intel-graphics-compiler-1.0.12504.6/debian/patches/series 2022-12-06 09:21:09.000000000 +0000 +++ intel-graphics-compiler-1.0.12504.6/debian/patches/series 2023-11-17 12:34:30.000000000 +0000 @@ -1,4 +1,5 @@ -#placeholder -fix-spirv-check.diff +0001-Preinstalled-SPIRV-Tools-CMakeFile-fix.patch +0002-Changed-relative-paths-in-include-directives.patch +0003-Add-multi-indirect-byte-regioning-feature.patch +0004-VC-subtarget-refactoring.patch #typos.patch -fix-relative-includes.patch